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FEMTOCLOCKSTM CRYSTAL-TO3.3V, 2.5V LVPECL CLOCK GENERATOR
ICS843021I-01 Features
* * * * * * * *
One differential 3.3V or 2.5V LVPECL output Crystal oscillator interface designed for 25MHz, 18pF parallel resonant crystal Output frequency range: 125MHz, using a 25MHz crystal VCO range: 490MHz - 640MHz RMS phase jitter @ 125MHz, using a 25MHz crystal (1.875MHz - 20MHz): 0.41ps (typical) Full 3.3V or 2.5V operating supply -40C to 85C ambient operating temperature Available in both standard (RoHS 5) and lead-free (RoHS 6) packages
General Description
The ICS843021I-01 is a Gigabit Ethernet Clock Generator and a member of the HiPerClocksTM HiPerClockSTM family of high performance devices from IDT. The ICS843021I-01 uses a 25MHz crystal to synthesize 125MHz. The ICS843021I-01 has excellent phase jitter performance, over the 1.875MHz - 20MHz integration range. The ICS843021I-01 is packaged in a small 8-pin TSSOP, making it ideal for use in systems with limited board space.
ICS
Block Diagram
OE Pullup
25MHz
Pin Assignment
VCC XTAL_OUT XTAL_IN VEE 1 2 3 4 8 7 6 5 Q nQ VCC OE
XTAL_IN
OSC
XTAL_OUT
Phase Detector
VCO
/4 (fixed)
Q nQ
/20 (fixed)
ICS843021I-01 8 Lead TSSOP 4.40mm x 3.0mm x 0.925mm package body G Package Top View
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Table 1. Pin Descriptions
Number 1, 8 2, 3 4 5 7, 8 Name VCC XTAL_OUT XTAL_IN VEE OE nQ, Q Power Input Power Input Output Pullup Type Description Power supply pins. Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output. Negative supply pin. Active high output enable. When logic HIGH, the outputs are enabled and active. When logic LOW, the outputs are disabled and are in a high impedance state. LVCMOS/LVTTL interface levels. Differential output pair. LVPECL interface levels.
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol CIN RPULLUP Parameter Input Capacitance Input Pullup Resistor Test Conditions Minimum Typical 4 51 Maximum Units pF k
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Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Supply Voltage, VCC Inputs, VI Outputs, IO Continuos Current Surge Current Package Thermal Impedance, JA Storage Temperature, TSTG Rating 4.6V -0.5V to VCC+ 0.5V 50mA 100mA 129.5C/W (0 mps) -65C to 150C
DC Electrical Characteristics
Table 3A. Power Supply DC Characteristics, VCC = 3.3V 5%, VEE = 0V, TA = -40C to 85C
Symbol VCC IEE Parameter Positive Supply Voltage Power Supply Current Test Conditions Minimum 3.135 Typical 3.3 Maximum 3.465 64 Units V mA
Table 3B. Power Supply DC Characteristics, VCC = 2.5V 5%, VEE = 0V, TA = -40C to 85C
Symbol VCC IEE Parameter Positive Supply Voltage Power Supply Current Test Conditions Minimum 2.375 Typical 2.5 Maximum 2.625 62 Units V mA
Table 3C. LVCMOS/LVTTL DC Characteristics, VCC = 3.3V 5% or 2.5V 5%, VEE = 0V, TA = 0C to 70C
Symbol VIH Parameter Input High Voltage Test Conditions VCC = 3.3V VCC = 2.5V Input Low Voltage Input High Current Input Low Current VCC = 3.3V VCC = 2.5V VCC = VIN = 3.465 or 2.625V VCC = 3.465V or 2.625V, VIN = 0V -150 Minimum 2 1.7 -0.3 -0.3 Typical Maximum VCC + 0.3 VCC + 0.3 0.8 0.7 5 A A Units V V V
VIL IIH IIL
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Table 3D. LVPECL DC Characteristics, VCC = 3.3V 5%, VEE = 0V, TA = -40C to 85C
Symbol VOH VOL VSWING Parameter Output High Current; NOTE 1 Output Low Current; NOTE 1 Peak-to-Peak Output Voltage Swing Test Conditions Minimum VCC - 1.4 VCC - 2.0 0.6 Typical Maximum VCC - 0.9 VCC - 1.7 1.0 Units A A V
NOTE 1: Outputs termination with 50 to VCC - 2V.
Table 3E. LVPECL DC Characteristics, VCC = 2.5V 5%, VEE = 0V, TA = -40C to 85C
Symbol VOH VOL VSWING Parameter Output High Current; NOTE 1 Output Low Current; NOTE 1 Peak-to-Peak Output Voltage Swing Test Conditions Minimum VCC - 1.4 VCC - 2.0 0.4 Typical Maximum VCC - 0.9 VCC - 1.5 1.0 Units A A V
NOTE 1: Outputs termination with 50 to VCC - 2V.
Table 4. Crystal Characteristics
Parameter Mode of Oscillation Frequency; NOTE 1 Equivalent Series Resistance (ESR) Shunt Capacitance Drive Level Test Conditions Minimum Typical Fundamental 25 90 7 300 MHz Maximum Units
pF W
AC Electrical Characteristics
Table 5A. AC Characteristics, VCC = 3.3V 5%, VEE = 0V, TA = -40C to 85C
Parameter fOUT tjit(O) tR / tF odc Symbol Output Frequency RMS Phase Jitter, Random; NOTE 1 Output Rise/Fall Time Output Duty Cycle 125MHz, ( Integration Range: 1.875MHz - 20MHz) 20% to 80% 250 49 Test Conditions Minimum 122.5 Typical 125 0.41 600 51 Maximum 160 Units MHz ps ps %
NOTE 1: Please refer to Phase Noise Plot.
Table 5B. AC Characteristics, VCC = 2.5V 5%, VEE = 0V, TA = -40C to 85C
Parameter fOUT tjit(O) tR / tF odc Symbol Output Frequency RMS Phase Jitter, Random; NOTE 1 Output Rise/Fall Time Output Duty Cycle 125MHz, ( Integration Range: 1.875MHz - 20MHz) 20% to 80% 250 49 Test Conditions Minimum 122.5 Typical 125 0.42 600 51 Maximum 160 Units MHz ps ps %
NOTE 1: Please refer to Phase Noise Plot.
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Typical Phase Noise at 125MHz (3.3V or 2.5V)
0 -10 -20 -30 -40 -50 -60 dBc Hz -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 100 1k 10k 100k Offset Frequency (Hz) 1M 10M 100M 125MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz (3.3V)= 0.41ps (typical) 1.875MHz to 20MHz (2.5V)= 0.42ps (typical)
Noise Power
Raw Phase Noise Data
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Phase Noise Result by adding a Gigabit Ethernet filter to raw data
ICS843021AGI-01 REV. A DECEMBER 3, 2007
Gigabit Ethernet Filter
ICS843021I-01 FEMTOCLOCKSTMCRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR
Parameter Measurement Information
2V 2V
VCC
Qx
SCOPE
VCC
Qx
SCOPE
LVPECL
nQx VEE
LVPECL
nQx VEE
-1.3V 0.165V
-0.5V 0.125V
3.3V LVPECL Output Load AC Test Circuit
2.5V LVPECL Output Load AC Test Circuit
Phase Noise Plot Noise Power
80%
Phase Noise Mask
80% VSW I N G
Clock Outputs
20% tR tF
20%
f1
Offset Frequency
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
RMS Phase Jitter
Output Rise/Fall Time
nQ Q
t PW
t
PERIOD
odc =
t PW t PERIOD
x 100%
Output Duty Cycle/Pulse Width/Period
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Application Information
Crystal Input Interface
The ICS843021I-01 has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 1 below were determined using a 25MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error. The optimum C1 and C2 values can be slightly adjusted for different board layouts.
X1 18pF Parallel Crystal XTAL_OUT C2 27p
XTAL_IN C1 27p
Figure 1. Crystal Input Interface
LVCMOS to XTAL Interface
The XTAL_IN input can accept a single-ended LVCMOS signal through an AC coupling capacitor. A general interface diagram is shown in Figure 2. The XTAL_OUT pin can be left floating. The input edge rate can be as slow as 10ns. For LVCMOS inputs, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. This configuration requires that the output impedance of the driver (Ro) plus the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50 applications, R1 and R2 can be 100. This can also be accomplished by removing R1 and making R2 50.
VCC
VCC
R1 Ro Rs 50 0.1f XTAL_IN
Zo = Ro + Rs
R2
XTAL_OUT
Figure 2. General Diagram for LVCMOS Driver to XTAL Input Interface
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Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
3.3V Zo = 50 125 FOUT FIN Zo = 50 FOUT 50 1 Z ((VOH + VOL) / (VCC - 2)) - 2 o 50 VCC - 2V RTT Zo = 50 84 84 FIN 125
Zo = 50
RTT =
Figure 3A. 3.3V LVPECL Output Termination
Figure 3B. 3.3V LVPECL Output Termination
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Termination for 2.5V LVPECL Outputs
Figure 4A and Figure 5B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50 to VCC - 2V. For VCC= 2.5V, the VCC- 2V is very close to ground level. The R3 in Figure 4B can be eliminated and the termination is shown in Figure 4C.
2.5V 2.5V 2.5V VCC = 2.5V R1 250 50 + 50 - - R3 250 50 + VCC = 2.5V
50
2.5V LVPECL Driver
R1 50 R2 50
2.5V LVPECL Driver
R2 62.5 R4 62.5
R3 18
Figure 4A. 2.5V LVPECL Driver Termination Example
Figure 4B. 2.5V LVPECL Driver Termination Example
2.5V VCC = 2.5V
50 +
50 -
2.5V LVPECL Driver
R1 50 R2 50
Figure 4C. 2.5V LVPECL Driver Termination Example
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Schematic Example
Figure 5 shows an example of ICS843021I-01 application schematic. In this example, the device is operated at VCC = 3.3V. The decoupling capacitor should be located as close as possible to the power pin. The input is driven by a 25MHz quartz crystal. For the LVPECL output drivers, only two termination examples are shown in this schematic. Additional termination approaches are shown in the LVPECL Termination Application Note.
VCC = 3.3V 3.3V
C2 27pF X1 25MHz S)
U1 Zo = 50 Ohm 1 2 3 4 VCC XTAL_OUT XTAL_IN VEE 843021I-01 Q nQ VCC OE 8 7 6 5
R3 133
R5 133
+ OE Zo = 50 Ohm -
C1 27pF
R4 82.5
R6 82.5
VCC
C3 10uF
C4 .1uF
C5 .1uF
Zo = 50
+
Zo = 50
-
R2 50
R1 50
R3 50
Optional Termination
Figure 5. ICS843021I-01 Schematic Example Figure 5. ICS843021I-01 Schematic Example
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Power Considerations
This section provides information on power dissipation and junction temperature for the ICS843021I-01. Equations and example calculations are also provided.
1.
Power Dissipation.
The total power dissipation for the ICS843021I-01 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. * * Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 64mA = 221.76mW Power (outputs)MAX = 30mW/Loaded Output pair
Total Power_MAX (3.3V, with all outputs switching) = 221.76mW + 30mW = 251.76mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS devices is 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 129.5C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 0.252W * 90.5C/W = 117.6C. This is below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (single layer or multi-layer).
Table 6. Thermal Resistance JA for 8 Lead TSSOP, Forced Convection
JA by Velocity Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 129.5C/W 1 125.5C/W 2.5 123.5C/W
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3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 6.
VCC
Q1
VOUT
RL 50
VCC - 2V
Figure 6. LVPECL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of VCC - 2V.
* * For logic high, VOUT = VOH_MAX = VCC_MAX - 0.9V (VCC_MAX - VOH_MAX) = 0.9V For logic low, VOUT = VOL_MAX = VCO_MAX - 1.7V (VCC_MAX - VOL_MAX) = 1.7V
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low.
Pd_H = [(VOH_MAX - (VCC_MAX - 2V))/RL] * (VCC_MAX - VOH_MAX) = [(2V - (VCC_MAX - VOH_MAX))/RL] * (VCC_MAX - VOH_MAX) = [(2V - 0.9V)/50] * 0.9V = 19.8mW
Pd_L = [(VOL_MAX - (VCC_MAX - 2V))/RL] * (VCC_MAX - VOL_MAX) = [(2V - (VCC_MAX - VOL_MAX))/RL] * (VCC_MAX - VOL_MAX) = [(2V - 1.7V)/50] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
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Reliability Information
Table 7. JA vs. Air Flow Table for a 8 Lead TSSOP
JA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 129.5C/W 1 125.5C/W 2.5 123.5C/W
Transistor Count
The transistor count for ICS843021I-01 is: 1765
Package Outline and Package Dimension
Package Outline - G Suffix for 8 Lead TSSOP Table 8. Package Dimensions
All Dimensions in Millimeters Symbol Minimum Maximum N 8 A 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 2.90 3.10 E 6.40 Basic E1 4.30 4.50 e 0.65 Basic L 0.45 0.75 0 8 aaa 0.10 Reference Document: JEDEC Publication 95, MO-153
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Ordering Information
Table 9. Ordering Information
Part/Order Number ICS843021AGI-01 ICS843021AGI-01T ICS843021AGI-01LF ICS843021AGI-01LFT Marking 1AI01 1AI01 AI01L AI01L Package 8 Lead TSSOP 8 Lead TSSOP "Lead-Free" 8 Lead TSSOP "Lead-Free" 8 Lead TSSOP Shipping Packaging Tube 2500 Tape & Reel Tube 2500 Tape & Reel Temperature 0C to 70C 0C to 70C 0C to 70C 0C to 70C
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
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(c) 2007 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA

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